1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, requiring highly doped shallow junctions formed on the basis of resist masks.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence to obtain a high dopant concentration having a profile that varies laterally and in depth.
Generally, the ion implantation process is a viable technique for introducing certain dopant species, such as P-type dopants, N-type dopants and the like, into specified device areas, which are usually defined by appropriate implantation masks, such as resist masks and the like. During the definition of active transistor regions, such as P-wells and N-wells, and during the formation of the actual drain and source dopant profiles, respective resist masks are typically provided to selectively expose and cover the device areas to introduce the required type of dopant species. That is, the respective implant species is introduced into non-covered device portions while the resist material blocks the dopant species and prevents dopant penetration into covered device portions, wherein the average penetration depth is determined by the implantation energy for a given implant species and a given material composition of the device area, while the dopant concentration is determined by the implantation dose and the implantation duration. Thereafter, the resist mask is removed and a further implantation process may be performed according to device requirements on the basis of a newly formed resist mask. Hence, a plurality of implantation processes are to be performed during the formation of transistor elements, thereby also requiring a plurality of resist removal processes. Due to the demand for extremely shallow junctions, i.e., drain/source dopant profiles, in particular in portions located in the vicinity of the channel region, which are also referred to as drain/source extensions, moderately low implantation energies at high doses are to be used, thereby resulting in specific difficulties during the resist removal process, as will be described with reference to FIGS. 1a-1b in more detail.
FIG. 1a schematically illustrates a cross sectional view of a conventional semiconductor device 100 during a manufacturing stage, in which appropriate dopant profiles are to be selectively formed in active areas of transistor elements. The semiconductor device 100 comprises a substrate 101, which may represent any appropriate carrier material for forming therein or thereon respective circuit elements, such as transistors, capacitors and the like. For example, the substrate 101 may represent a silicon bulk substrate or a silicon-on-insulator (SOI) substrate, since the vast majority of complex integrated circuits, such as CPUs, storage chips and the like, are and will be in the foreseeable future formed on the basis of silicon. The device 100 may further comprise a corresponding semiconductor layer 102, which may represent a silicon layer and the like, in which may be defined, for instance on the basis of isolation structures 103, a first device region 110 and a second device region 120, which may, for instance, correspond to respective active areas of transistor elements to be formed in and on the first and second device regions 110, 120. Furthermore, in the manufacturing stage shown in FIG. 1a, respective gate electrodes 111, 121 may be formed above the material of the semiconductor layer 102 and may be separated therefrom by respective gate insulation layers 113 and 123, respectively. As previously explained, in highly sophisticated semiconductor devices, the ongoing shrinkage of feature sizes may demand a gate length, i.e., in FIG. 1a, the horizontal extension of the gate electrodes 111, 121, of 50 nm and significantly less, thereby also necessitating sophisticated dopant profiles in the first and second device areas 110, 120. Furthermore, the gate electrodes 111, 121 may have formed thereon a corresponding sidewall spacer structure 112, 122, which may act as an implantation mask for laterally profiling the dopant concentration to be formed in the semiconductor material of the first and second device regions 110, 120. Moreover, the device 100 comprises a resist mask 104, which covers the first device region 110 and exposes the second device region 120 to an ion bombardment of a respective implantation process 105.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following processes. After providing the substrate 101 having formed thereon the semiconductor layer 102, possibly including a buried insulating layer (not shown) when an SOI configuration is considered, the first and the second device regions 110, 120 may be defined by forming the isolation structures 103. For this purpose, well-established techniques may be used, including photolithography, anisotropic etch, deposition and polishing techniques, for forming the isolation structures 103 in the form of shallow trench isolations. Thereafter, an appropriate masking regime may be used in order to selectively cover the first and the second device regions 110, 120 for establishing appropriate vertical dopant profiles in order to establish basic transistor characteristics, such as the conductivity type of the transistor under consideration, the threshold voltage thereof and the like. The corresponding implantation sequences may be performed on the basis of well-established process parameters, such as implantation energy, implantation dose and the like, wherein, typically, the required dopant concentrations may be significantly less compared to the dopant concentrations required during the definition of PN junctions in the device regions 110, 120. Consequently, moderately low implantation doses may be used in combination with appropriate implantation energies, thereby maintaining the interaction of the implant species with the corresponding resist materials at a low level, thus allowing the removal of the corresponding resist materials after implantation on the basis of well-established plasma or wet chemical etch processes.
Thereafter, the gate insulation layers 113, 123 may be formed on the basis of well-established oxidation and/or deposition processes followed by the patterning of the gate electrodes 111, 121, wherein respective lateral dimensions thereof may be adjusted to the above-specified range. Next, the sidewall spacer structures 112, 122 may be formed by well-established techniques, such as the deposition of an appropriate material followed by an anisotropic etch process, oxidation techniques and the like. It should be appreciated that, in this manufacturing stage, a respective screen or pad layer may also be formed above the first and second device regions 110, 120, for instance in the form of an oxide layer, in order to protect exposed surfaces of the semiconductor material of the layer 102 and enhancing the subsequent implantation process 105. For convenience, any such layers are not shown in FIG. 1a. 
Thereafter, the resist mask 104 may be formed on the basis of photolithography techniques and, subsequently, the device 100 may be subjected to the implantation process 105, which may be designed to obtain a shallow dopant profile 124, which may represent an extension region of a corresponding drain and source region still to be formed in a later manufacturing stage. As previously explained, the extension regions 124 may require a moderately high dopant concentration, thereby necessitating high implantation dose values in order to obtain the desired high dopant concentration at an acceptable process time. Since only a very restricted average penetration depth is required for the extension regions 124, which may be several nanometers and even less for highly sophisticated semiconductor devices, the corresponding implantation energies may range from several keV (kilo electron volts) to 1 keV or less depending on the type of dopant species, the thickness of a corresponding pad layer, if provided, the type of semiconductor material and the like. Consequently, the ion bombardment during the implantation 105 may cause significant damage on exposed surface portions of the resist mask 104, thereby creating a crust layer 104A, which may comprise carbonized resist material imparting significantly different mechanical and chemical characteristics to the basic resist material of the mask 104. For example, the crust layer 104A, having a high density compared to the substantially non-implanted resist material 104B, may cause a significantly different behavior during well-established plasma-based or wet chemical etch processes for removing resist material, thereby typically requiring additional reactive components in order to first etch the resist crust layer 104A prior to completely removing the residual resist material 104B. The additional etch chemistry may, however, have a significant influence on surface portions exposed to the corresponding reactive ambient, such as semiconductor material, dielectric material and the like.
FIG. 1b schematically illustrates the semiconductor device 100 during a conventional resist strip process 106 in order to efficiently remove the resist mask 104, wherein the process 106 may be configured as a plasma process based on oxygen and a further reactive component, such as fluorine in the form of carbon hexa fluoride, in order to etch through the crust layer 104A. During the exposure to the ambient of the process 106, exposed surface portions 125 within the second device region 120 may be damaged by the reactive components contained in the ambient of the process 106, thereby resulting in a significant material removal. For instance, carbon fluoride is well known to remove silicon, silicon dioxide, and the like during a corresponding plasma-based process, which may thus result in a significant amount of material loss in respective exposed device areas, which may impose significant issues during further manufacturing stages with respect to appropriately adjusting the overall transistor characteristics, in particular when highly scaled devices are considered. For example, a material loss of up to a thickness of approximately 2 nm, as indicated by the dashed line, may occur during the process 106 and subsequent chemical cleaning processes for removing any residuals of the resist mask 104, which may not be acceptable for devices of 65 nm technologies and beyond. In particular, the significant material loss of exposed device areas may not only result in corresponding thickness fluctuations, depending on the specific process conditions in the various device regions 110, 120, but may also result in a significant loss of dopants, thereby directly influencing the transistor performance. Consequently, on the one side, well-established oxygen plasma etch processes for stripping resist materials may no longer be appropriate due to the creation of the highly stable crust layer 104A, while, on the other hand, adding additional reactive components, such as carbon fluorine, may contribute to a significant material loss and, thus, a potential dopant loss, which may result in significant process non-uniformity and device degradation when highly scaled semiconductor devices are considered.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.